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ccd60 back illuminated electron multiplying ccd sensor introduction the ccd60 is part of the new l3vision 2 range of products from e2v technologies. this device uses a novel output amplifier circuit that is capable of operating at an equivalent output noise of less than one electron at frame rates of 1 khz. the sensor is a frame transfer device, designed for high frame rate applications such as wavefront sensing or adaptive optics. the device operates in inverted mode to suppress dark current. a variant exists to provide image section antiblooming. the e2v technologies back-thinning process ensures high quantum efficiency over a wide range of wavelengths. the device functions by converting photons to charge in the image area during the integration time period, then transferring this charge through the image and store sections into the readout register. following transfer through the readout register, the charge is multiplied in the gain register prior to conversion to a voltage by a low noise output amplifier. the multiplication gain may be varied by adjustment of the multiplication phase amplitude r 1 2hv. general data active image area ........ 3.072 x 3.072 mm image section active pixels ..... 128(h)x128(v) image pixel size ............24x24 m m number of output amplifiers .......... 1 fill factor ............... 100% package details (nominal, see fig. 14) ceramic package 24-pin dil overall dimensions ......... 32.9 x 20.1 mm number of pins .............. 24 inter-pin spacing ......... 2.54 + 0.15 mm opposite row spacing ....... 15.24 + 0.25 mm window material ...... quartz or removable glass mounting position ............. any pin 1 is identified as shown in fig. 14. storage and operation temperature extremes min max storage temperature ( 8 c) 7 200 +100 operating temperature ( 8 c) 7 120 +75 temperature ramping ( 8 c/min) C 5 note: operation or storage in humid conditions may give rise to ice on the sensor surface on cooling, causing irreversible damage. # e2v technologies limited 2004 a1a-ccd60bi issue 5, may 2004 411/8320 e2v technologies limited, waterhouse lane, chelmsford, essex cm1 2qu england telephone: +44 (0)1245 493493 facsimile: +44 (0)1245 492492 e-mail: enquiries@e2vtechnologies.com internet: www.e2vtechnologies.com holding company: e2v holdings limited e2v technologies inc. 4 westchester plaza, po box 1482, elmsford, ny10523-1482 usa telephone: (914) 592-6050 facsimile: (914) 592-5148 e-mail: enquiries@e2vtechnologies.us
typical performance specifications the following are for operation of devices at 500 hz frame rate and at typical operating voltages. parameters are given at 293 k unless specified otherwise. where parameters are different in the normal and high gain mode, both are given. parameter unit min typical max output amplifier responsivity (normal mode) (see note 1) m v/e 7 C 1.2 C multiplication register gain (see notes 2, 3 and 4) 1 C 1000 peak signal - non-inverted mode operation (see note 5): non-antibloomed antibloomed e 7 /pixel e 7 /pixel C C 530k 260k C C peak signal - inverted mode operation: non-antibloomed antibloomed e 7 /pixel e 7 /pixel C C 240k 130k C C charge handling capacity of multiplication register (see note 6) e 7 /pixel C 800k C readout noise at 11 mhz (normal mode) (see note 7) e 7 rms C 100 C readout noise at 11 mhz (high gain mode) e 7 rms C 5 1C integrated dark signal at 293 k (see note 8) e 7 /pixel/s C 900 C integrated dark signal non-uniformity (dsnu) at 293 k (see notes 8 and 9) e 7 /pixel/s C 3400 C excess noise factor (see note 10) C h 2C maximum readout frequency (settling to 1%) (see notes 5 and 11) mhz C 11 18 maximum parallel transfer frequency mhz C 10 C notes 1. measured at a pixel rate of 1 mhz. 2. the typical variation of gain with r 1 2hv is shown in fig. 1. 3. the typical variation of gain with r 1 2hv at different temperatures is shown in fig. 1. 4. some increase of r 1 2hv may be required throughout life to maintain gain performance. adjustment of r 1 2hv should be limited to the maximum specified under operating conditions. 5. these values are predicted from design and not measured. 6. when multiplication gain is used, a linear response of output signal with input signal is achieved for output signals up to typically 400 ke 7 . 7. these noise values are dominated by reset noise in the output amplifier and it is assumed that correlated double sampling (cds) is not being implemented. if cds is used to suppress the reset component, a noise of 10 e 7 can typically be achieved at a pixel rate of 1 mhz with a noise floor of 4 e 7 rms. at 11 mhz the noise with cds is about 35 e 7 . these values are inferred by design and not measured. 8. the quoted dark signal has the usual temperature dependence for inverted mode operation. for operation at high frame rates with short integration times, the dark signal will be dominated by an additional component generated during readout. operating at a temperature of 293 k and 500 hz frame rate, the readout component contributes typically 3.6 e 7 /pixel/frame at a gain of 1000 and referred to the image area, and has a temperature dependence consistent with non-inverted mode operation. there exists a further weakly temperature dependent component, the clock induced charge, which is independent of the integration time and is a function of the operating biases and timings employed. for more information, refer to the e2v technologies technical note: "dark signal and clock-induced charge in l3vision tm ccd sensors". 9. dsnu is defined as the 1 s variation of the dark signal. 10. the excess noise factor is defined as the factor by which the multiplication process increases the shot noise on the image when multiplication gain is used. 11. a maximum readout frequency of 18 mhz is expected to be achievable with a 20 pf load, output settling to 1%, and single sampling. ordering information part number operating mode antiblooming coating window ccd60-01-*-b89 2-phase imo none midband temporary ccd60-00-*-108 2-phase imo shielded midband temporary ccd60bi, page 2 # e2v technologies
1000 100 10 1 39 40 41 42 43 44 45 46 r 1 2hv multiplication gain t = 293 k t = 273 k t = 253 k t = 233 k t = 223 k 8067a device cosmetic performance grade 1 devices are supplied to the blemish specification shown below. note that incorrect biasing of the device may result in spurious dark or white blemishes appearing. these will be eliminated if the biases are adjusted. test conditions operating mode device run in 2-phase inverted mode at a rate of 500 frames/second. sensor temperature 22 + 3 8 c. multiplication gain set to approximately 1000. illumination set to give a signal level of approximately 50 e 7 /pixel/frame. blemish specification black columns black defects are counted when they have a responsivity of less than 80% of the local mean signal at approximately the specified multiplication gain and level of illumination. a black column contains at least 9 contiguous black defects. white columns white defects are pixels having a dark signal generation rate corresponding to an output signal of greater than 5 times the maximum specified dark signal level. a white column contains at least 9 contiguous white defects. pin-head columns pin-head columns are manifest as a partial dark column with a bright pixel showing photoresponse at the end of the column nearest to the readout register. pin-head columns are counted when the black column has a responsivity of less than 80% of the local mean signal at approximately the specified multiplication gain and level of illumination. a pin-head column contains at least 9 black defects. specification for grade 1 devices parameter specification white columns 0 black columns 0 pin-head columns 0 figure 1: typical variation of multiplication gain with r 1 2hv at different temperatures # e2v technologies ccd60bi, page 3
100 90 80 70 60 50 40 30 20 10 0 300 400 500 600 700 800 900 1000 wavelength (nm) quantum efficiency (%) 8239 figure 2: typical variation of integrated dark signal with temperature (no window, t = 20 8 c) figure 3: typical spectral response, midband coated (at +20 8 c, no window) ccd60bi, page 4 # e2v technologies 10 7 1 10 7 2 1 10 10 2 10 3 10 4 dark signal (e 7 /pixel/s) package temperature ( 8 c) 7 40 7 20 0 20 40 7407a
absolute maximum ratings maximum ratings are with respect to ss. pin connection min (v) max (v) 1s 1 2 7 20 +20 2s 1 1 7 20 +20 3 abd 7 0.3 +28 4ig 7 20 +20 5i 1 1 7 20 +20 6ss 0 7 1 r 7 20 +20 8ss 0 9* os 7 0.3 +25 10 od 7 0.3 +32 11 r 1 dc 7 20 +20 12 r 1 2hv 7 20 +50 13 rd 7 0.3 +25 14 og 7 20 +20 15 r 1 2 7 20 +20 16 r 1 1 7 20 +20 17 r 1 3 7 20 +20 18 r 1 1 7 20 +20 19 r 1 2 7 20 +20 20 dg 7 20 +20 21 s 1 2 7 20 +20 22 s 1 1 7 20 +20 23 i 1 2 7 20 +20 24 s 1 1 7 20 +20 * permanent damage may result if, in operation, os experiences short-circuit conditions. maximum voltages between pairs of pins: pin connection pin connection min (v) max (v) 10 od 9 os 7 15 +15 12 r 1 2hv 11 r 1 dc 7 20 +50 12 r 1 2hv 11 r 1 dc 7 20 +50 12 r 1 2hv 17 r 1 3 7 20 +50 output transistor current (ma) 20 esd handling procedures ccd sensors, in common with most high performance ic devices, are static sensitive. in certain cases a static electricity discharge may destroy or irreversibly degrade the device. accordingly, full anti-static handling precautions should be taken whenever using a ccd sensor or module. these include: * working at a fully grounded workbench. * operator wearing a grounded wrist strap. * all receiving socket pins to be positively grounded. * unattended ccds should not be left out of their conducting foam or socket. all devices are provided with internal protection circuits to most gate electrodes but not to the other pins. evidence of incorrect handling will terminate the warranty. exposure to radiation exposure to radiation may irreversibly damage the device and result in degradation of performance. users wishing to operate the device in a radiation environment are advised to consult e2v technologies. # e2v technologies ccd60bi, page 5
operating conditions typical operating voltages are as given in the table below. some adjustment within the minimum-maximum range specified may be required to optimise performance. connection pulse amplitude or dc level (v) min typical max i 1 1,2 high +4 (see note 12) +5 +7 (see note 12) i 1 1,2 low C 7 5C s 1 1,2 high +4 (see note 12) +5 +7 (see note 12) s 1 1,2 low C 7 5C r 1 1,2,3 high +10 +12 +13 r 1 1,2,3 low C 0 C r 1 2hv high +20 +40 +50 (see note 4) r 1 2hv low 0 +4 +5 1 r high +10 (see note 13) +12 +13 (see note 13) 1 r low C 0 C r 1 dc +2 +3 +5 og +1 +3 +5 ss 0 +4.5 +7 od +25 +28 +32 rd +15 +18 +20 ig C 7 5C abd: non-antibloomed devices antibloomed devices +20 +10 +24 +15 +27 +20 dg low: non-antibloomed devices antibloomed devices C C 0 7 5 C C dg high: non-antibloomed devices antibloomed devices +10 C +12 7 5 +15 C notes 12. i 1 and s 1 adjustment may be common. 13. 1 r high level may be adjusted in common with r 1 1,2,3. 14. for non-antibloomed devices, it is possible dump unwanted lines of signal by employing the timing diagram in fig. 10. dg high should be 2 v greater than r 1 1,2,3 high. charge is dumped from the standard register (see fig. 11) into abd. users of shielded antibloomed devices wishing to dump unwanted lines are advised to contact e2v technologies. an external load is required. this can either be a resistor of about 2.2 k o (non-critical) or a constant current type of about 7.5 ma. the total on-chip power dissipation at 500 hz frame rate is approximately 200 C 250 mw, depending on the details of the voltages and clock timings used. ccd60bi, page 6 # e2v technologies
drive pulse waveform specification the following are suggested pulse rise and fall times for operation at 500 hz frame rate, and with pixel readout at 11 mhz. clock pulse typical rise time (ns) typical fall time (ns) typical pulse overlap i 1 20 20 @90% points s 1 20 20 @90% points r 1 1 5 5 @70% points r 1 2 5 5 @70% points r 1 3 5 5 @70% points r 1 2hv 25 25 see note 16 r 1 2hv sine sine sinusoid- high on falling edge of r 1 1 notes 15. register clock pulses are as shown in figs. 4 and 5. 16. an example clocking scheme is shown in fig. 5. r 1 2hv can also be operated with a normal clock pulse, as shown in fig. 4. the requirement for successful clocking is that r 1 2hv reaches its maximum amplitude before r 1 1 goes low. electrical interface characteristics electrode capacitances at mid clock levels connection capacitance to ss inter-phase capacitances total capacitance units i 1 1 (see note 17) 750 100 850 pf i 1 2 (see note 17) 750 100 850 pf s 1 1 (see note 17) 750 100 850 pf s 1 2 (see note 17) 750 100 850 pf r 1 1 364177pf r 1 2 564197pf r 1 3 62 60 122 pf r 1 2hv 45 49 94 pf series resistances connection approximate total series resistance i 1 19 o i 1 29 o s 1 19 o s 1 29 o r 1 17 o r 1 27 o r 1 37 o r 1 2hv 8 o amplifier output impedance 250 o note 17. for operation in the inverted mode. for operation in the non-inverted mode, the capacitance to substrate is 400 pf and the total capacitance is 500 pf. # e2v technologies ccd60bi, page 7
r 1 2hv r 1 1 r 1 2 r 1 3 8237 figure 4: clocking scheme for multiplication gain (normal clock pulses) figure 5: clocking scheme for multiplication gain (sine wave clocks) ccd60bi, page 8 # e2v technologies r 1 2hv r 1 1 r 1 2 r 1 3 8238
1 r r 1 3 t 1 t w t 2 8055 pulse timings and overlaps figure 6: reset pulse t w = 10 ns typical t 1 = output valid t 2 4 0ns figure 7: pulse and output timing # e2v technologies ccd60bi, page 9 r 1 3 1 r os reset feedthrough signal output vos 8069
s 1 1 136 cycles s 1 2 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r 8 overscan pixels 128 signal pixels non-imo 8070a figure 8: example line timing diagram figure 9: example frame timing diagram ccd60bi, page 10 # e2v technologies i 1 1 i 1 2 s 1 1 s 1 2 r 1 1 r 1 2 r 1 3 r 1 2hv 1 r 4 136 r 1 cycles 130 i 1 /s 1 cycles readout of first line through amplifier 134 lines min transfer of first line to register non-imo extended 1st pulse at start of frame transfer, 4 2 m s typically 8071a
r 1 1 r 1 2 r 1 3 dg s 1 1 s 1 2 n line transfer cycles 4 10 m s 4 2.5 m s 4 0.5 m s 8235 figure 10: operation of the dump gate to dump n lines of unwanted data from the standard register (non-antibloomed devices only, see note 14) figure 11: schematic chip diagram # e2v technologies ccd60bi, page 11 123456789101112 13 14 15 16 17 18 19 20 21 22 23 24 s 1 1i 1 2s 1 1s 1 2dgr 1 2r 1 1r 1 3r 1 1r 1 2og rd r 1 2hv r 1 dc od os ss 1 r ss i 1 1 ig abd s 1 1 s 1 2 image section 128 columns 130 rows store section 128 columns 130 rows standard register 128 elements 1st multiplication register 128+8+128 elements 2nd multiplication register 128 elements 3rd multiplication register 128 elements register bends 8 elements each register overscan 8 elements 8112c
og rd 1 r s 1 1 (internal connection) od substrate ss 0 v output external load os r 1 3 r 1 2 r 1 1 c n 8061 figure 12: line output format note 18. there is a 4-line propagation delay between transferring a line from the store section to the standard register and reading it out through the output amplifier. figure 13: output circuit schematic ccd60bi, page 12 # e2v technologies 8 overscan 128 active outputs 8236
a b imaging area package centre m d e d image plane f g h j k l n pin 1 c 8115 figure 14: package outline (all dimensions without limits are nominal) ref millimetres a 32.9 + 0.4 b 20.1 + 0.3 c 3.30 + 0.35 d 3.072 e 0.1 + 0.5 f 0.26 + 0.04 g 15.24 + 0.25 h 2.305 + 0.600 j 4.85 min k 2.54 + 0.15 l 27.94 + 0.15 m 4.76 + 0.50 n 0.46 + 0.20 printed in england # e2v technologies ccd60bi, page 13 whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences o f any use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond that set out in i ts standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information cont ained herein.

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